In general, a multilayer wiring structure of a semiconductor device is formed by burying a metal wiring in a groove of an interlayer insulating film. The metal wiring is typically made of a material containing copper (Cu) having low electromigration and low electric resistance. When using the material containing Cu, a (diffusion) barrier layer made of tantalum (Ta) or tantalum nitride (TaN) is used to suppress copper from being diffused into an underlying layer.
Recently, various developments have been made for the purposes of improving reliability of the barrier layer. To this end, a self-formation barrier layer using a manganese (Mn) film or a CuMn alloy film, instead of a Ta film or TaN film, is attracting attention (see, for example, Patent Document 1).    Patent Document 1: Japanese Patent Laid-open Publication No. 2005-277390    Patent Document 2: Japanese Patent Laid-open Publication No. 2011-066274
In a method described in Patent Document 1, for example, a Cu film is formed on an insulating film and, then, a Mn-containing film is formed thereon in order to form a self-formation barrier layer. When burying Cu in a groove portion (trench or via hole) of the insulating film, however, it may be difficult to bury the Cu with high coverage through a PVD method in case of forming a fine wiring having a trench width equal to or less than, e.g., about 50 nm. Furthermore, since the Cu is in direct contact with the insulating film for a long time, the Cu may be diffused into the insulating film.